1. Technical Field of the Invention
The present invention relates to a clock shaping circuit, which receives a clock signal containing jitters and outputs a clock signal with reduced jittering and, in particular, to a clock shaping circuit having a PLL (Phase Locked Loop).
2. Description of the Related Art
To meet a high data rate, an oscillator in electronic equipment such as a communication apparatus must stably oscillate at a high frequency region (with a high frequency stability) and within a practical temperature range (with a temperature compensation).
Communication apparatuses use a clock signal when transmitting or receiving data. In this case, the clock signal must be free from jitters. To obtain a stable and jitter-free clock signal, a clock shaping circuit 10 incorporating a PLL circuit is used as shown in FIGS. 17 and 18.
FIG. 17 is a block diagram generally illustrating a conventional clock shaping circuit.
This clock shaping circuit is widely referred to as a jitter-reducing circuit. The clock shaping circuit is also referred to as a dejittering circuit, a jitter clean-up circuit, or a clock smoothing circuit. A PLL circuit having a voltage-controlled oscillator (a clock generator) is used. In response to a clock signal S1 input thereto containing jittering, a clock shaping circuit 1 outputs a clock signal S3 with the jittering thereof reduced.
In the clock shaping circuit, the voltage-controlled oscillator may employ a voltage-controlled SAW (Surface Acoustic Wave) oscillator VCSO using a SAW resonator, or a voltage-controlled liquid-crystal oscillator (VCXO) to improve phase noise and jitter characteristics.
The clock shaping circuit 10 shown in FIG. 18 includes a phase comparator 3, a loop filter 2, a voltage-controlled oscillator VCSO/VCXO 4, a buffer 9, and a feedback loop (hereinafter simply referred to as a closed loop) of a PLL circuit.
The phase comparator 3 in the clock shaping circuit 10 thus constructed compares the phase of the clock signal S1 containing jitters with the phase of the feedback clock signal (hereinafter referred to as a comparison clock signal) S2 fed back from the VCSO/VCXO 4, and outputs a control signal responsive to the results of the comparison. The output is then subjected a smoothing process through the loop filter 2, and is then applied to a voltage control terminal of the VCSO/VCSO 4, thereby controlling the oscillation of the VCSO/VCSO 4.
Although the clock signal S1 contains a jittering component, the buffer 9 outputs a clock signal with the level of jittering thereof lowered because the loop bandwidth of the PLL circuit limits the frequency component of the jitter.
Conventional clock shaping circuits typically employ an LC-VCO, composed of an inductance and a capacitor, used as the VCO 4, or a ring oscillator. For this reason, the conventional clock shaping circuits suffer from poor phase noise characteristics and poor jitter characteristics, and is unable to reduce jitters.
To improve phase noise and jitter characteristics, one clock shaping circuit employs a voltage-controlled crystal oscillator VCXO or a voltage-controlled SAW oscillator VCSO with a SAW resonator, as a voltage-controlled oscillator VCO shown in FIG. 19.
The SAW resonator is one which makes use of the property of an elastic body that concentrates and propagates energy near the surface of the body. Interdigital transducers are disposed on a piezoelectric substrate. A surface acoustic wave excited by the transducers are reflected, generating a standing wave. The assembly thus functions as a resonator. The SAW resonator oscillates within a frequency range from several tens of MHz to several hundreds of MHz. In terms of frequency-temperature characteristics and costs, this resonator is less preferable than an AT cut quartz crystal resonator.
Interfacing such as impedance matching in an input/output interface and a transmission line (a wiring line for interconnection in this case) is somewhat difficult in terms of the transfer of a clock signal in the above construction in a high frequency region of several hundreds of MHz. The input and output sides adversely affect each other, thereby lowering an output amplitude level of a signal. In case of a differential output, the amplitudes of output signals between a positive output terminal and a negative output terminal are unbalanced, and a phase difference occurs between the two terminals.
To avoid the problem, a known clock shaping circuit shown in FIG. 20 includes, as a separate integrated circuit (hereinafter referred to as an IC), an output buffering driver IC (a buffer 9) attached to the output of a voltage-controlled crystal oscillator VCXO or a voltage-controlled SAW oscillator VCSO. The addition of the output buffering driver IC increases a component count, and a compact design is difficult to implement in the clock shaping circuit.
There are times when, for some reason, the conventional clock shaping circuit suffers from an interruption of the supply of the clock signal S1 from the outside, a substantial change in the frequency thereof, and an out-of-lock state in the phase and frequency. In such a case, a closed loop enters a free run condition. The clock shaping circuit fails to output a stable clock signal having excellent phase noise and jitter characteristics. If data is transferred based on that clock signal, data transfer malfunctions.
The reasons why the output clock signal loses its stability in the free-run state are that a control signal applied to the VCO 4 is not appropriate, and that the frequency varies due to the temperature characteristics of the VCO 4. If the VCO 4 is formed of a voltage-controlled oscillator LC-VCO composed of a capacitor and inductance, a ring oscillator, or a voltage-controlled SAW oscillator having a SAW resonator, an inconvenience of frequency variation due to a change in temperature becomes large.
The present invention has been developed to resolve the above problem, and it is an object of the present invention to provide a clock shaping circuit, which does not directly affect a clock signal when the output of the voltage-controlled quartz crystal oscillator VCXO, or the voltage-controlled SAW oscillator VCSO, is used as a feedback loop output., and which is free from an unbalance of an output amplitude and a phase difference in differential outputs between positive and negative output terminals.
It is another object of the present invention to provide a clock shaping circuit, which has a smaller component count with no output buffering driver IC required, and is easy to miniaturize.
It is yet another object of the present invention to provide a clock shaping circuit, which outputs a clock signal with less jitters even when an out-of-lock state occurs for some reason.
It is a further object of the present invention to provide a clock shaping circuit, which includes a voltage-controlled SAW oscillator exhibiting improved frequency-temperature characteristics regardless of a change in temperature.
It is still a further object of the present invention to provide electronic equipment, which continuously operates without interruption with a clock shaping circuit thereof assuring a clock signal containing less jittering even when the clock shaping circuit is unlocked for some reason.
A clock shaping circuit of a first aspect includes a clock generator, which changes a frequency of an output comparison clock signal in response to a supplied control voltage, a phase comparator, which generates a phase difference signal based on the results of comparison of the comparison clock signal from the clock generator with an input signal from the outside, and a loop filter for smoothing the phase difference signal, wherein the clock generator includes a positive feedback oscillation loop including, at least, a piezoelectric resonator, an oscillation differential amplifier, a feedback buffering differential amplifier, and a voltage-controlled phase shifter for shifting a phase by a predetermined amount in response to the control voltage, and wherein the output signal from the feedback buffering differential amplifier is the comparison clock signal.
In accordance with the first invention, the output signal from either a non-inverting output terminal and or an inverting output terminal of the feedback buffering differential amplifier in the clock generator is used as a feedback loop output, which means the comparison clock signal. Because this structure is adopted, there is no unbalance of the output amplitudes and the phase difference of the outputs of the non-inverting and the inverting terminals for the differential amplifier.
A clock shaping circuit of a second invention includes a clock generator, which changes a frequency of an output comparison clock signal in response to a supplied control voltage, a phase comparator, which generates a phase difference signal based on the results of the comparison of the comparison clock signal from the clock generator with an input signal from the outside, and a loop filter for smoothing the phase difference signal, wherein the clock generator includes a positive feedback oscillation loop including, at least, a piezoelectric resonator, a voltage-controlled phase shifter, and an oscillation amplifier, and further a plurality of output amplifiers, and wherein the comparison clock signal is the output signal from one of the plurality of output amplifiers, which branch the output signal of the oscillation amplifier.
In accordance with the second aspect, one of the output signals from one of the plurality of output amplifiers, which branch the output signal of the oscillation amplifier, is used as the comparison clock signal. This arrangement prevents the output amplitude from dropping in level, thereby eliminating the need for connecting an output buffering driver IC to the output of the clock generator. The clock shaping circuit becomes compact in design with the component count thereof reduced.
In a clock shaping circuit of a third aspect, the feedback buffering differential amplifier has a non-inverting output terminal and an inverting output terminal, one of the output terminals has the function of outputting the comparison clock signal and the other of the output terminals has the function of outputting a positive feedback oscillation loop output.
In accordance with the third aspect, one of the two output terminals of the feedback buffering differential amplifier serves as the comparison clock signal output terminal and the other of the two output terminals serves as the positive feedback oscillation loop output terminal. In this arrangement, one single feedback buffering differential amplifier is used as a feedback loop and a positive feedback loop.
In a clock shaping circuit of a fourth aspect, each of the oscillation differential amplifier and the feedback buffering differential amplifier is a differential amplifier employing an ECL line receiver.
Since the ECL line receiver is a differential amplifier circuit having non-inverting and inverting differential outputs in accordance with the fourth aspect, a clock shaping circuit operates at a low power consumption and at a high speed.
In a clock shaping circuit of a fifth aspect, the phase comparator includes, at least, a first divider means for frequency-dividing the input signal from the outside, and a second divider means for frequency-dividing the comparison clock signal.
In accordance with the fifth aspect, the phase comparator circuit in the phase comparator includes the first divider and the second divider, each having a respective predetermined divide-by ratio, and low frequency outputs provided by the phase comparator circuit are compared. This arrangement permits the use of a low speed IC. A low-cost and highly accurate phase comparator thus results.
In a clock shaping circuit of a sixth aspect, the piezoelectric resonator is a SAW resonator.
In accordance with the sixth aspect, the SAW resonator is used as the piezoelectric resonator. A high-frequency output is thus easy to obtain.
In a clock shaping circuit of a seventh aspect, the piezoelectric resonator is a quartz crystal resonator.
Since an oscillation source of the clock shaping circuit is a AT cut quartz crystal oscillator in accordance with the seventh aspect, a highly stable output is obtained.
A clock shaping circuit of an eighth aspect includes a phase comparator, which compares an input clock signal with a comparison clock signal in phase, and outputs a signal responsive to the results of the comparison, a quartz crystal oscillator circuit, which generates a backup clock signal having a predetermined frequency corresponding to the input clock signal, a backup phase comparator, which compares, in phase, the backup clock signal generated by the quartz crystal oscillator circuit with the comparison clock signal and outputs a signal responsive to the results of the comparison, an out-of-lock detector, which detects a phase out-of-lock state based on the input clock signal and the comparison clock signal, a selector, which selects and outputs either the output signal of the phase comparator or the output signal of the backup phase comparator in response to the detection of the out-of-lock detector, a loop filter, which performs a smoothing process on the output signal selected by the selector, and a clock generator, which generates the comparison clock signal while varying the frequency of the comparison clock signal in accordance with the output signal of the loop filter.
In accordance with the eighth aspect, if a main closed loop is unlocked after the input of the clock signal from the outside is interrupted for some reason or after jittering in the clock signal becomes large in level, the main closed loop is changed to a backup closed loop. The comparison clock signal from the VCSO/VCSO and a backup clock signal from the quartz crystal oscillator are used.
Even if the main closed loop enters a free run condition for some reason, a clock signal remains stable and has less jittering.
In a clock shaping circuit of a ninth aspect, the quartz crystal oscillator circuit is a temperature-compensated quartz crystal oscillator circuit.
In accordance with the ninth aspect, the use of the temperature-compensated quartz crystal oscillator circuit provides the clock signal having stable temperature characteristics even under severe temperature conditions.
In a clock shaping circuit of a tenth aspect, the backup phase comparator includes a divider, which frequency-divides the comparison clock signal generated by the clock generator, and the backup phase comparator compares, in phase, the predetermined backup clock signal generated by the quartz crystal oscillator circuit and the output signal of the divider, and outputs a signal responsive to the results of the comparison.
In accordance with the tenth aspect, the divider in the backup phase comparator frequency-divides the comparison clock signal generated by the clock generator down to the range of the predetermined backup clock signal generated by the quartz crystal oscillator circuit. Since the backup phase comparator compares the two frequencies in a low frequency range, a low-speed IC works and is used. A low-cost and high-precision phase comparator is thus manufactured.
In a clock shaping circuit of an eleventh aspect, the clock generator includes a voltage-controlled SAW oscillator circuit.
In accordance with the eleventh aspect, the use of the SAW resonator as a piezoelectric resonator easily results in an output of high frequency.
A clock shaping circuit of a twelfth aspect, the clock generator includes a voltage-controlled quartz crystal oscillator circuit.
In accordance with the twelfth aspect, the use of the quartz crystal resonator as a piezoelectric resonator assures a clock signal having stable temperature characteristics.
A clock shaping circuit of a thirteenth aspect includes a phase comparator, which compares, in phase, an input clock signal with a comparison clock signal, and outputs a signal responsive to the results of the comparison, a quartz crystal oscillator circuit, which generates a backup clock signal having a predetermined frequency corresponding to the input clock signal, a backup phase comparator, which compares, in phase, the backup clock signal generated by the quartz crystal oscillator circuit with the comparison clock signal and outputs a signal responsive to the results of the comparison, a first loop filter, which performs a smoothing process on the output signal of the phase comparator, a second loop filter, which performs a smoothing process on the output signal of the backup phase comparator, an out-of-lock detector, which detects a phase out-of-lock state based on the input clock signal and the comparison clock signal, a selector, which selects and outputs either the output signal of the first loop filter or the output signal of the second loop filter, in response to the detection of the out-of-lock detector, and a clock generator, which generates the comparison clock signal while varying the frequency of the comparison clock signal in accordance with the output signal selected by the selector.
In accordance with the thirteenth aspect, if the closed loop is unlocked, the main closed loop is switched to a closed loop that uses the backup clock signal generated by the quartz crystal oscillator circuit. In this arrangement, the two loop filters including the second loop filter are arranged, and low frequency characteristics appropriate for the closed loops, routed in the phase comparator and the backup phase comparator respectively, are set for the two loop filters. The closed loop becomes thus stable, thereby resulting in a more stable clock signal.
In a clock shaping circuit of a fourteenth aspect, the quartz crystal oscillator circuit is a temperature-compensated quartz crystal oscillator circuit.
In accordance with the fourteenth aspect, the use of the temperature-compensated quartz crystal oscillator circuit provides the clock signal having stable temperature characteristics even under severe temperature conditions.
In a clock shaping circuit of a fifteenth aspect, the backup phase comparator compares, in phase, the output signal, which is obtained by frequency-dividing the comparison clock signal generated by the clock generator by the divider, with the predetermined backup clock signal generated by the quartz crystal oscillator circuit, and outputs a signal responsive to the results of the comparison.
In accordance with the fifteenth aspect, the divider in the backup phase comparator frequency-divides the comparison clock signal generated by the clock generator down to the range of the predetermined backup clock signal generated by the quartz crystal oscillator circuit. Since the backup phase comparator compares the two frequencies in a low frequency range, a low-speed IC is used. A low-cost and high-precision backup phase comparator is thus manufactured.
In a clock shaping circuit of a sixteenth aspect, the clock generator includes a voltage-controlled SAW oscillator circuit.
In accordance with the sixteenth aspect, the use of the SAW resonator as a piezoelectric resonator easily results in an output of high frequency.
In a clock shaping circuit of a seventeenth aspect, the clock generator includes a voltage-controlled quartz crystal oscillator circuit.
In accordance with the seventeenth aspect, the use of the quartz crystal resonator as a piezoelectric resonator assures a clock signal having stable temperature characteristics.
In a clock shaping circuit of an eighteenth aspect, the phase comparator includes a phase comparator circuit and a first charge pump, which converts the output of a phase comparator circuit into a DC voltage corresponding to a phase difference of an input signal to the phase comparator, and the backup phase comparator includes a backup phase comparator circuit and a second charge pump, which converts the output of a phase comparator circuit into a DC voltage corresponding to a phase difference of an input signal to the phase comparator.
In accordance with the eighteenth aspect, the phase comparator includes the phase comparator circuit and the charge pump having a simple structure, and the backup phase comparator includes the backup phase comparator circuit and the charge pump having a simple structure. A low-cost phase comparator and a low-cost backup phase comparator are easily manufactured.
In a clock shaping circuit of a nineteenth aspect, a first digital signal processor (DSP) is substituted for the first charge pump and the first loop filter, and a second digital signal processor (DSP) is substituted for the second charge pump and the second loop filter.
In accordance with the nineteenth aspect, the DSP substituted for the loop filter permits digital processing, and a substantially compact design is implemented. Noise resistance to external noise is thus improved.
A clock shaping circuit of a twentieth aspect includes a phase comparator, which compares, in phase, an input clock signal with a comparison clock signal, and outputs a signal responsive to the results of the comparison, a loop filter, which performs a smoothing process on the output signal of the phase comparator, a voltage output circuit, which outputs a predetermined voltage responsive to the output signal of the loop filter, an out-of-lock detector, which detects a phase out-of-lock state based on the input clock signal and the comparison clock signal, a selector, which selects and outputs either the output signal of the loop filter or the output signal of the voltage output circuit in response to the detection of the out-of-lock detector, and a clock generator, which generates the comparison clock signal while varying the frequency of the comparison clock signal in accordance with the output signal selected by the selector.
In accordance with the twentieth aspect, the main closed loop is disengaged and the VCSO is supplied with the output of the voltage output circuit when the standard closed circuit is unlocked during the operation of the clock shaping circuit. The frequency-temperature characteristics of the VCSO are improved by imparting temperature dependency to the constant voltage of the voltage output circuit to cancel the effect of temperature in the temperature characteristics of the VCSO in a low temperature region and a high temperature region (temperature compensation).
In a clock shaping circuit of a twenty-first aspect, the clock generator includes a voltage-controlled SAW oscillator circuit.
In accordance with the twenty-first aspect, the use of a SAW resonator as a piezoelectric resonator easily results in a high-frequency output.
In a clock shaping circuit of a twenty-second aspect, the clock generator includes a voltage-controlled quartz crystal oscillator circuit.
In accordance with the twenty-second aspect, the use of a quartz crystal resonator as a piezoelectric resonator assures a clock signal having reliable temperature characteristics.
In a clock shaping circuit of a twenty-third aspect, the phase comparator includes a charge pump, which converts the output of a phase comparator circuit into a DC voltage responsive to the phase difference of an input signal to the phase comparator.
In accordance with the twenty-third aspect, a low-cost phase comparator is easily manufactured because the phase comparator is formed of the phase comparator circuit and the charge pump having a simple structure.
In a clock shaping circuit of a twenty-fourth aspect, a digital signal processor (DSP) is substituted for the charge pump and the loop filter.
In accordance with the twenty-fourth aspect, the DSP substituted for the loop filter permits digital processing. Therefor a substantially compact design is possible to implement. Noise resistance to external noise is thus improved.
A clock shaping circuit of a twenty-fifth aspect, the voltage output circuit sets the predetermined voltage to any voltage at a variable level.
In accordance with the twenty-fifth aspect, the voltage output circuit immediately responds to an out-of-lock state by setting the output voltage thereof to be variable when the closed loop is unlocked in response to an excessively enlarged jitter in the clock signal.
In a clock shaping circuit of a twenty-sixth aspect, the output voltage of the voltage output circuit has a temperature-dependent property so that the oscillation output of the clock generator is temperature compensated.
In accordance with the twenty-sixth aspect, the frequency-temperature characteristics of the VCSO are improved by imparting temperature dependency to the constant voltage of the voltage output circuit to cancel the effect of temperature in the temperature characteristics of the VCSO in a low temperature region and a high temperature region (temperature compensation).
The clock shaping circuit thus constructed of the present invention continuously outputs a desired clock signal having reduced jittering even if the supply of the clock signal from the outside is interrupted or even if the closed loop is unlocked as a result of excessive jittering in the clock signal. Specifically, the clock shaping circuit of the present invention uses the quartz crystal oscillator by switching to the backup closed loop when the main closed loop enters a free run condition for some reason. A stable clock signal with reduced phase noise and reduced jittering thus results.
In a clock shaping circuit of a twenty-seventh aspect, the clock generator in the clock shaping circuit includes a piezoelectric resonator, an oscillation differential amplifier, a feedback buffering differential amplifier, and a voltage-controlled phase shifter for shifting a phase by a predetermined amount in response to a control voltage, a positive feedback oscillation loop is formed of, at least, the piezoelectric resonator, the oscillation differential amplifier, the feedback buffering differential amplifier, and the voltage-controlled phase shifter, and the output signal of the feedback buffering differential amplifier is the comparison clock signal.
In accordance with the twenty-seventh aspect, either the outputs from the non-inverting output terminal or the inverting-output terminal of the feedback buffering differential amplifier in the clock generator is used as a feedback loop output. This arrangement prevents the signals from the output terminals from affecting each other, thereby avoiding a drop in level of the output amplitude. The unbalanced output amplitude and the phase difference between the non-inverting output terminal and the inverting output terminal of the differential amplifier are avoided.
In a clock shaping circuit of a twenty-eighth aspect, the clock generator in the clock shaping circuit includes a piezoelectric resonator, an oscillation amplifier, a voltage-controlled phase shifter for shifting a phase by a predetermined amount in response to a control voltage, and a plurality of output amplifiers, a positive feedback oscillation loop is formed of, at least, the piezoelectric resonator, the voltage-controlled phase shifter, and the oscillation amplifier, and the comparison clock signal is the output signal from one of the plurality of output amplifiers, which branch the output signal of the oscillation amplifier.
In accordance with the twenty-eighth aspect, the output signal of the oscillation amplifier is branched into a plurality of signals through the plurality of output amplifiers, and one of the output signals is used as the comparison clock signal. This arrangement eliminates the need for an external buffering driver IC, and prevents the output signal and the comparison clock signal from affecting each other. This arrangement thus requires no external components, avoiding an increase in component count, and thus leading to a compact design.
If the external output buffering driver IC is used, the phase difference occurs between the output signals due to the wiring for interconnection between the output amplifier and the buffer circuit. However, the phase difference is eliminated through the use of the plurality of output amplifiers, which branch the output signal from the oscillation amplifier, in the IC.
In a clock shaping circuit of a twenty-ninth aspect, the feedback buffering differential amplifier has a non-inverting output terminal and an inverting output terminal, one of the output terminals has the function of outputting the comparison clock signal and the other of the output terminals has the function of outputting a positive feedback oscillation loop output.
In accordance with the twenty-ninth aspect, either the non-inverting output terminal or the inverting output terminal of the feedback buffering differential amplifier in the clock generator functions as an output terminal for outputting the comparison clock signal and the other of the output terminals functions as an output terminal for outputting the positive feedback oscillation loop output signal. This arrangement eliminates the unbalance and the phase difference in the output amplitude between the non-inverting output and the inverting output in the differential amplifier.
In a clock shaping circuit of a thirtieth aspect, each of the oscillation differential amplifier and the feedback buffering differential amplifier is a differential amplifier employing an ECL line receiver.
In accordance with the thirtieth aspect, a high-speed and power saving clock shaping circuit is obtained by using the ECL line receiver to the differential amplifier.
In a clock shaping circuit of a thirty-first aspect, the phase comparator includes a first divider, which frequency-divides the input signal from the outside, a second divider, which frequency-divides the comparison clock signal, and a phase comparator circuit, which compares the phases of the output signals of the first divider and the second divider.
In accordance with the thirty-first aspect, the phase comparator includes the first and second dividers, each having a respective divide-by ratio, and the phase comparator circuit compares the low frequencies provided by the respective dividers. Using a low-speed IC, a low-cost and high precision phase comparator is provided.
In a clock shaping circuit of a thirty-second aspect, the piezoelectric resonator is a SAW resonator.
In accordance with the thirty-second aspect, the use of a SAW resonator as a piezoelectric resonator results in a high-frequency output.
In a clock shaping circuit of a thirty-third aspect, the piezoelectric resonator is a quartz crystal resonator.
In accordance with the thirty-third aspect, the use of a temperature-compensated AT cut quartz crystal resonator having no temperature-dependence as an oscillation source in the clock shaping circuit results in a reliable output.
Electronic equipment of a thirty-fourth aspect includes a clock shaping circuit of one of the first through thirty-third aspects.
In accordance with the thirty-fourth aspect, the clock shaping circuit of the thirty-fourth aspect is applied in electronic equipment such as an optical transceiver module. A clock with reduced jittering is provided in contrast to a received clock signal having large jittering resulting from a demultiplexer in the module. A timing margin is assured between received data and the clock signal. An erratic operation of a multiplexer in the optical transceiver module is thus prevented.
If the clock shaping circuit having the out-of-lock detector circuit of the present invention is incorporated in electronic equipment, a clock signal with less jittering is assured even when the clock shaping circuit is unlocked. With that clock signal, a variety of operations of the electronic equipment are continuously performed without interruptions.